The present invention relates to a semiconductor device and a manufacturing technology thereof, and particularly to a semiconductor device wherein a semiconductor chip is mounted over a wiring board and external coupling terminals are provided at a surface (back surface) opposite to a semiconductor chip mounting surface (front surface) of the wiring board, and a technology effective if applied to the manufacture of the semiconductor device.
A technique related to a BGA (Ball Grid Array) which prevents the formation of bores or dimples in via holes defined in a wiring substrate or board has been described in Japanese Unexamined Patent Publication No. 2006-190928 (patent document 1). In this technique, vias (blind vias) that do not extend through the wiring board are formed inside the wiring board. Lands (pads) are formed at the back surface of the wiring board so as to be directly coupled to the vias respectively. Namely, a so-called Pad on via structure has been disclosed in which each of the vias is disposed over its corresponding land formed at the back surface of the wiring board. At this time, the ends of the lands formed at the back surface of the wiring board are covered with a solder resist, and openings that open the solder resist are formed at their corresponding central portions of the lands. That is, each of the lands described in the patent document 1 has a so-called SMD (Solder Mask Defined) structure wherein the diameter of each opening defined in the solder resist is smaller than the diameter of each land, and the opening is formed so as to be internally contained in its corresponding land in plan view. Solder balls are mounted onto their corresponding lands each brought to the SMD structure thereby to form the BGA.
In Japanese Unexamined Patent Publication No. 2002-368154 (patent document 2), vias that extend through a wiring board are formed and lands (pads) are formed at the back surface of the wiring board so as to be directly coupled to the vias respectively. Namely, a so-called pad on via structure has been disclosed even in the patent document 2. At this time, a package targeted in the patent document 2 is of an LGA (Land Grid Array) and is configured in such a manner that a solder resist is not applied onto the back surface of the wiring board.